TTL信號(hào)或 LVDS信號(hào) 32位; 200MHz高速數(shù)字I/O卡

生產(chǎn)廠商： 迪陽(yáng)公司代理 產(chǎn)品型號(hào)： PCIe-HPDI32ALT
產(chǎn)品簡(jiǎn)介： TTL信號(hào)或 LVDS信號(hào) 32位; 200MHz高速數(shù)字I/O卡，數(shù)字時(shí)鐘速率：50MHz/s,

售價(jià)：￥0

Features

200 Mbytes per second (max) input transfer rate via the front panel connector (TTL I/O transceivers)
200 Mbytes per second input transfer rate via the front panel connector (LVDS transceivers)
264 Mbytes per second PCI transfer rate in burst mode.
A single board can interface to a wide variety of external high-speed devices.
"Deep FIFO buffers" (up to 512 Kbytes) allow data bursts to be transferred over the PCI bus independent of transfers over the cable.
64-Bit data transfers on the PCI bus.
On-board cable controller, FIFOs, and DMA engine provide for continuous data transfer capability.
Data input/output clock rate up to 50 MHz
Data input/output width of 32 bits
64-Bit, 66MHz PCI v2.2 compliant
"Program-and-forget" DMA engine handles D64 transfers, also DMA Chaining
Sample code, Vx Works©, Windows 98©, Windows 2000©, Windows XP©, Linux©, Lab VIEW©, and Windows NT© drivers are available
Interrupts available upon DMA-completion, FIFO status, cable status, frame-valid and line-valid.
External interrupt input line
7 bi-directional signals can be user defined and programmed by the factory to accommodate almost any handshaking protocol (Contact factory).

	Description

The PCIe-HPDI32ALT board is a flexible bi-directional 32-bit digital I/O board that transmits and receives data from 20 Mbytes (TTL I/O) to 200 Mbytes (LVDS) per second. The board is useful as a general-purpose DMA interface to a variety of external peripherals.

The DMA engine is capable of transferring data to/ from Host memory using D32 block transfers, while the FIFO memory (up to One Mbyte of total FIFO) provides continuous transmission of data without interrupting the DMA transfers or requiring intervention from the Host CPU. The board has 7 bi-directional programmable handshake lines and eight preconfigured software selectable interface protocols to allow easy interfacing to most digital I/O peripherals.

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